ECE 5/411 CMOS Analog IC Design
Spring 2011, Boise State University
Lecture notes are here.
Homework assignments, project information, and due dates are located here.
Current grades are here.
Cadence tutorials for ECE511 are provided here and the Wiki with FAQs is here.
Instructor : Vishal Saxena
Time : Monday, Wednesday, 6:00-7:15 p.m.
Course dates : Jan 19 – May 4, 2011.
Location : MEC 206
Office Hours : Monday, Wednesday, 4:30-5:30 p.m.
Holidays : March 28 & 30.
Final Exam time: Monday,
May 9, 2011, 6:00-8:00 p.m.
Course TA : Sakkarapani Balagopal (Bala), Email: sakkarapanibalagopal@u.boisestate.edu
Textbook – CMOS Circuit Design, Layout and Simulation – R. J. Baker, 3nd Edition, Wiley-IEEE, 2010.
For detailed references and handouts see this page.
Course content – Current
mirrors, voltage references, negative feedback systems and stability,
amplifiers, frequency compensation, opamps.
PREREQ: ECE 5/410.
For Graduate credit (ECE 511): A more complex design project will be assigned and additional homework and exam problems may be given.
CAD software information
The course will require extensive use of Cadence Design System in Linux environment. Set up your account to remotely use Cadence:
1. Setup
guidelines for remote access (Nomachine) to the Linux servers are here.
2. Cadence configuration steps are listed here.
3. Spectre models for the TSMC 180nm CMOS process are here.
The course Google group is (http://groups.google.com/group/ams-bsu) and the email address is ams-bsu@googlegroups.com
Workload (Grading)
20% Midterm1
20% Midterm2
20% Homeworks
20% Project
20% Final
Policies
No late work accepted. All assigned work is due at the beginning of class.
Neither the final exam nor final project will be returned at the end of the semester.
Cheating or plagiarism will result in an automatic F grade in the course (so do your own homework and projects!)